Modern high-density integrated circuits (ICs) are known to be vulnerable to damage from the electrostatic discharge (ESD) from a charged body (human or otherwise) as the charged body physically contacts the IC. ESD damage occurs when the amount of charge exceeds the capability of the electrical conduction path through the IC. The typical ESD failure mechanisms include thermal runaway resulting in junction shorting, and dielectric breakdown resulting in gate-junction shorting in the metal-oxide-semiconductor (MOS) context.
An IC may be subjected to a damaging ESD event in the manufacturing process, during assembly, testing, or in the system application. In conventional IC ESD protection schemes, active clamp circuits are generally used to shunt ESD current between the power supply rails and thereby protect internal IC element nodes that are connected to bond pads from ESD damage.
Conventional vertical NPN bipolar devices used for ESD protection of devices on an IC typically include a surface n-type region (e.g., surface nwell) on an n+ sinker diffusion that is on an n+ buried layer (NBL) which together provides a collector in one or more device stripes (or fingers) to provide a low resistance-path to carry ESD strike induced current back to the top surface (e.g., top of the surface nwell). In BiMOS technologies, it is a common practice to use such vertical NPN devices for the ESD protection circuitry.
For ESD protection of ESD sensitive pins, the clamping device is generally needed to not snap back below the rated supply voltage during the ESD strike. ESD NPN bipolar devices can be used for this purpose. In BiMOS technologies conventional vertical ESD NPN devices originally designed for 15V operation can be modified to reverse the emitter and collector pins to access the lower breakdown voltage of the n+ source/drain (NSD)-surface pwell (SPWELL) junction for collector-base junction breakdown. In addition, a conventional deep pwell diffusion can be added to increase the p-side doping level of the SPWELL to further reduce the collector-base junction breakdown voltage to provide about a 5V breakdown voltage.